PDF Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

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lecture8 - Current mode logic - Latch design

Approaches to push the energy efficiency limits are discussed to allow ubiquitous adoption and uninterrupted hardware protection. Although often ignored, cost is a major factor that decides whether a security feature is incorporated in real-world systems or not. To gain an insight into cost, the implications at all phases of the chip lifecycle are examined, as opposed to simplistic analyses that focus only on the design time.

To further expand on the cost dimension, approaches to drastically reduce the design effort are discussed, pushing the design timescale down to hours. Finally, directions on how to manage and reduce the typically large design margin are discussed. He has authored or co-authored more than publications on journals and conference proceedings.


  • Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits.
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  • His primary research interests include self-powered wireless integrated systems, near-threshold circuits for green computing, energy-quality scalable integrated systems, data-driven integrated systems, hardware-level security, and emerging technologies, among the others.

    Thin Film Transistors Materials and Processes.


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